In the field of electronics, specific drive currents and drive voltages are required to drive electronic components in a variety of devices. Certain electronic devices require controllable constant current sources for them to provide the functionality desired.
Drive voltages and drive currents are higher, by many factors of magnitude, compared to the voltages and currents employed within integrated circuits for providing component control logic. For example, integrated circuits employ 1.8V and currents in the range of micro and pica amps to drive logic gates, while individual controlled components require voltages up to hundreds of volts (for example 90V are required by ink jet nozzles to operate) and currents in the range of ˜1 to 100 mA. Very often the number of components to be driven in an overall device requires combined currents in the range of amps. The circuit implementation area of a driver circuit increases as the drive current (and the drive voltage) increases. Large driving currents make it impossible to have a high density of driving circuits in one integrated circuit to control multiple components.
It is also desirable in many applications to finely control the amount of drive current delivered to each component. High current control resolution further limits the number of component control drivers that can be accommodated within an integrated circuit die area.
The present wisdom in the art provides for an array of transistors in parallel that can be switched on in any combinations to provide a current that is the sum of all the transistors that are turned on. Such circuits being referred to as Digital to Analog Controller (DAC) as the output current is a reflection of binary inputs.
An alternate circuit often used to provide variable control of electronic and electrical devices is the Pulse Width Modulation (PWM) circuit. Here the current is not a variable but the duty cycle is. The current is switched on at a high rate for variable time thus providing variable energy to the device being driven. A digital version of this PWM circuit is known as DPWM. In a DPWM circuit a clock external to the circuit is provided to two counters. First counter counts to form a pulse clock that determines the maximum time for the pulse. The second counter counts down the count of the pulse width provided by digital inputs. The number of bits represents the resolution of the control circuit. Therefore the number of pulses (per unit time) is determined by the first counter and the duration of the pulses is controlled by the second counter. The energy provided to the electronic or electrical device being driven is the integral over time of the current pulses.
Despite providing good current control resolution, employing large arrays of transistors drivers increases the circuit area of the integrated circuit current driver due to the need for a decoder and additional control traces to activate transistors in the transistor array. This means that both miniaturization and high control resolution cannot be achieved together.
The state of the art provides for an array of unit driver transistors in parallel, combinations of which can be switched on to provide a drive current that is the sum of the currents provided by all transistors turned on. Such current driver circuits are referred to as Digital-to-Analog Converter (DAC) as the output current is a reflection of a number of binary inputs.
An alternate driver circuit, often used to provide variable control of electronic and electrical devices, is the Pulse Width Modulation (PWM) circuit. PWM provide a constant output current however with a variable duty cycle. The output current is switched on at a high rate for variable time periods thus providing a variable amount of energy to the device being driven. In a “Digital” PWM (DPWM) circuit version, a clock external to the circuit is provided to increment two counters. A first counter counts the duration of a pulse clock which determines the maximum duration for each pulse in clock cycles. A second counter counts down the duration of the pulse width specified via the digital inputs. The number of digital input bits represents the resolution of the DPWM drive circuit. Therefore the number of pulses per unit time (repetition rate) is determined by the first counter and the duration each pulse is controlled by the second counter, where the amount of energy provided to the electronic or electrical component/device being driven is the integral over time of the constant current pulses.
Generally, component current drive for example with a current control resolution of ½n, requires 256 different current control values for n=8. A logic control circuit will require an 8 bit register to drive a corresponding component. Implementing a typical component current driver using “unit current drivers” requires a multilevel decoder to decode the 8 bits to provide individual unit current driver control lines to enable each unit current driver to output the appropriate current. This approach requires 256 transistors to implement all unit current drivers and approximately 8000 gates in the decoder and the 8 bit register. Not only is the number of gates very large, the interconnection of these gates also requires a large implementation area on an integrated circuit semiconductor substrate.
Alternatively, the PWM approach requires counters, gates and corresponding interconnection, however only a single additional transistor at the output, the transistor being rated for maximum current. The number of gates used in this alternate approach is less than the above solution, but PWM suffers from noise due to high level of switching required to achieve the PWM function and makes PWM circuits costly, difficult to design and fabricate.
Therefore the implementation of either of the above circuits in semiconductor integrated circuits undesirably requires a substantial implementation area on a semiconductor wafer thereby limiting the number of such drivers which can be contained in a given semiconductor die size.
The size of the die may be constrained by other factors such as the wafer level fabrication technology used, the pattern of the connections of the driven device and material constraints. For a given wafer level fabrication technology, the size of the circuit implementation area required depends largely on three factors: maximum output voltage, maximum current and resolution of current control. The maximum output voltage determines the size of a gap required between integrated circuit conducting features and circuit traces to avoid arcing therebetween. The maximum current defines the width of the circuit traces as the height of the circuit traces is limited by metal deposition technologies. These two factors are governed by natural properties of materials employed in wafer level fabrication and cannot be changed. The third factor is determined by device design requirements. If a device to be driven by the current driver circuit requires only a few levels of control, then the number of digital input control bits required is low. If the device requires higher resolution of control, then the number of digital input control bits required is high. For example, four level temperature control requires only 2 control bits, whereas a 1% control resolution will require 8 control bits. The number of control bits may grow slowly with control resolution, but the complexity of the implementation in electronic circuits increases by more than the power of 2, i.e. logarithmically, imposing severe constraints on the density of control circuits which can be implemented on one integrated circuit die of a particular size. As a general rule, this constraint is inherent to the two prior art control methods described above.
In particular, the density of connectivity of logic circuit components on an integrated circuit semiconductor die is a problem. As the number of control bits grows, the connectivity grows logarithmically. For example, employing the DAC unit driver transistor array with 2n parallel transistors described hereinabove, requires decoding of the n bit input into 2n individual transistor control bits to switch the transistors. The required decoding circuit not only increases in complexity logarithmically, but the implementation also requires increasing levels of logic control. The logic control levels increase due to the limitation of individual gates in the circuit to drive subsequent gates; this is referred to as “fan out”. Fan out of a given technology is limited. The higher the control resolution, the greater the decoding logic levels required. Similarly, employing a DPWM circuit to provide control of electronic or electrical components/devices, increasing number of bits which are fed into the two counters (or voltage controlled pulse width generators) to generate pulses of predetermined frequency but varying pulse widths (duty cycles) limits the connectivity density. The number of transistors required to implement this circuit is also large and grows larger with the increase in the control resolution required but not logarithmically. Therefore, the density of driver circuits which can be integrated into a given semiconductor die area is limited and is independent of the technology used to implement such circuits.
To appreciate the complexity of the digital circuits and therefore the semiconductor die area required for implementation of such circuits, it is advantageous to understand the reasons behind this fact.
The cell area of a decoder circuit is proportional to n3, where n is the digital number whose inverse is the resolution of control required. Furthermore, the complexity of digital circuits is defined by two terms C and D, where C is the circuit size measured in number of inverters (NOR and NOT gates) and D is the circuit depth. For example, with reference to John Savage, “Models of Computation”, Addison-Wesley, 1998, for n, the number of digital inputs (resolution):C(fn)≤2C(fn/2)+2n, where C(fn/2)≤(2n−1)2n andD(fn)≤2D(fn/2)+1, where D(fn/2)≤[log2n]+1.For n=8:C(fn)≤2(2n−1)2n+2n≤2(2×8−1)×256+256=2×15×256+256=30×256+256=7936D(fn)≤2D(fn/2)+1, where D(fn/2)≤[log2n]+1=3+1D(fn)≤2×4+1≤9and for n=9:C(fn)≤2(2n−1)2n+2n≤2(2×9−1)×512+256=2×17×512+512=17920D(fn)≤2D(fn/2)+1, where D(fn/2)≤[log2n]+1=3+1D(fn)≤2×4+1≤9.Calculating the implementation area required for the decoder circuit for n=8 employing 0.35 CMOS technology, with each inverter requiring 2 transistors and each transistor occupying 16 square microns, the area required on the semiconductor die is 253,952 square microns. Furthermore, the depth D of the logic circuit being 9 means that propagation delays and interconnects themselves pose a difficult challenge. It should be noted that it is not possible to use wafer level fabrication technology which provides smaller transistors as the output voltage constraints the minimum feature size and therefore limits the technology which can be used for transistor fabrication.
Similarly, to understand the complexity related to DPWM control circuits as described above, it should be noted that each DPWM control circuit requires two n bit counters and gates. Each counter requires 80*n and 3*n gates for a total of 83n transistors. For n=8 and 16 sq. microns per transistor, the implementation area required on the semiconductor circuit die is 10,624 sq. microns per DPWM circuit. A different method of DPWM, using delay lines, requires far more area for the delay lines, similarly constraining the density of these controlled current driver circuits on one semiconductor circuit die.
An application where devices to be driven are arranged in a dense array is known from international patent application publication WO2010/130051, published 18 Nov. 2010. As illustrated in FIG. 4 therein, LED devices 204 are driven from drivers in an electronic component 406. The array of LEDs 514 provides a light source for a scanning print head, as shown in FIG. 5. Arranging controllable constant current supply circuits in the area surrounding each connector pad 402 is a problem for the reasons described above.